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CHIPS Alliance @chipsalliance
Common Hardware for Interfaces, Processors and Systems
CHIPS Alliance
@chipsalliance · chipsalliance.org
About the organization
Common Hardware for Interfaces, Processors and Systems
Primary technologies & languages
Technical topics & focus areas
Participation years
Repositories on GitHublive from github.com/chipsalliance, ranked by starsAll 122 repos
Chisel: A Modern Hardware Design Language
355 open issues · good place to start if you want to contributeRocket Chip Generator
280 open issues · good place to start if you want to contributeVerible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
566 open issues · good place to start if you want to contributeRandom instruction generator for RISC-V processor verification
136 open issues · good place to start if you want to contributeVeeR EH1 core
21 open issues · good place to start if you want to contributeFlexible Intermediate Representation for RTL
176 open issues · good place to start if you want to contributeA template project for beginning new Chisel work
14 open issues · good place to start if you want to contributeCaliptra IP and firmware for integrated Root of Trust block
130 open issues · good place to start if you want to contributeSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux g
47 open issues · good place to start if you want to contributeFOSS Flow For FPGA
14 open issues · good place to start if you want to contribute